A 1.2V 30nm 3.2Gb/s/pin 4Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme - researchr publication authors

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Kyomin Sohn, Taesik Na, Indal Song, Yong Shim, Wonil Bae, Sanghee Kang, DongSu Lee, Hangyun Jung, Hanki Jeoung, Ki Won Lee, Junsuk Park, Jongeun Lee, ByungHyun Lee, Inwoo Jun, Juseop Park, Junghwan Park, Hundai Choi, Sanghee Kim, Haeyoung Chung, Young Choi, Dae-Hee Jung, Jang Seok Choi, Byung-Sick Moon, Jung Hwan Choi, Byungchul Kim, Seong-Jin Jang, Joo-Sun Choi, Kyungseok Oh. A 1.2V 30nm 3.2Gb/s/pin 4Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme. In 2012 IEEE International Solid-State Circuits Conference, ISSCC 2012, San Francisco, CA, USA, February 19-23, 2012. pages 38-40, IEEE, 2012. [doi]

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