A 100nm Double-Stacked 500MHz 72Mb Separate-I/O Synchronous SRAM with Automatic Cell-Bias Scheme and Adaptive Block Redundancy - researchr publication authors

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Kyomin Sohn, Young-Ho Suh, Young-Jae Son, Daesik Yim, Kang-Young Kim, Dae-Gi Bae, Ted Kang, Hoon Lim, Soon-Moon Jung, Hyun-Geun Byun, Young-Hyun Jun, Kinam Kim. A 100nm Double-Stacked 500MHz 72Mb Separate-I/O Synchronous SRAM with Automatic Cell-Bias Scheme and Adaptive Block Redundancy. In 2008 IEEE International Solid-State Circuits Conference, ISSCC 2008, Digest of Technical Papers, San Francisco, CA, USA, February 3-7, 2008. pages 386-387, IEEE, 2008. [doi]

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