Dinesh Somasekhar, Shih-Lien Lu, Bradley A. Bloechel, Greg Dermer, Konrad Lai, Sjeljar Borkar, Vivek De. A 10Mbit, 15GBytes/sec bandwidth 1T DRAM chip with planar MOS storage capacitor in an unmodified 150nm logic process for high-density on-chip memory applications. In Laurent Fesquet, Andreas Kaiser, Sorin Cristoloveanu, Michel Brillouët, editors, Proceedings of the 31st European Solid-State Circuits Conference, ESSCIRC 2005, Grenoble, France, 12-16 September 2005. pages 355-358, IEEE, 2005. [doi]
@inproceedings{SomasekharLBDLBD05,
title = {A 10Mbit, 15GBytes/sec bandwidth 1T DRAM chip with planar MOS storage capacitor in an unmodified 150nm logic process for high-density on-chip memory applications},
author = {Dinesh Somasekhar and Shih-Lien Lu and Bradley A. Bloechel and Greg Dermer and Konrad Lai and Sjeljar Borkar and Vivek De},
year = {2005},
doi = {10.1109/ESSCIR.2005.1541633},
url = {https://doi.org/10.1109/ESSCIR.2005.1541633},
researchr = {https://researchr.org/publication/SomasekharLBDLBD05},
cites = {0},
citedby = {0},
pages = {355-358},
booktitle = {Proceedings of the 31st European Solid-State Circuits Conference, ESSCIRC 2005, Grenoble, France, 12-16 September 2005},
editor = {Laurent Fesquet and Andreas Kaiser and Sorin Cristoloveanu and Michel Brillouët},
publisher = {IEEE},
isbn = {0-7803-9205-1},
}