Self-Assertion-Based Countermeasures Within a RISC-V Microprocessor for Coverage of Information Leakage Faults - researchr publication authors

researchr

You are not signed in
Sign in
Sign up

Idris Somoye, Tom J. Mannos, Brian Dziki, Jim Plusquellic. Self-Assertion-Based Countermeasures Within a RISC-V Microprocessor for Coverage of Information Leakage Faults. IEEE Trans. on CAD of Integrated Circuits and Systems, 43(6):1677-1690, June 2024. [doi]

This author has not been identified. Look up 'Idris Somoye' in GoogleThis author has not been identified. Look up 'Tom J. Mannos' in GoogleThis author has not been identified. Look up 'Brian Dziki' in GoogleThis author has not been identified. Look up 'Jim Plusquellic' in Google

runs on WebDSL