Idris Somoye, Tom J. Mannos, Brian Dziki, Jim Plusquellic. Self-Assertion-Based Countermeasures Within a RISC-V Microprocessor for Coverage of Information Leakage Faults. IEEE Trans. on CAD of Integrated Circuits and Systems, 43(6):1677-1690, June 2024. [doi]
@article{SomoyeMDP24,
title = {Self-Assertion-Based Countermeasures Within a RISC-V Microprocessor for Coverage of Information Leakage Faults},
author = {Idris Somoye and Tom J. Mannos and Brian Dziki and Jim Plusquellic},
year = {2024},
month = {June},
doi = {10.1109/TCAD.2024.3351592},
url = {https://doi.org/10.1109/TCAD.2024.3351592},
researchr = {https://researchr.org/publication/SomoyeMDP24},
cites = {0},
citedby = {0},
journal = {IEEE Trans. on CAD of Integrated Circuits and Systems},
volume = {43},
number = {6},
pages = {1677-1690},
}