Test Time Reduction of 3-D Stacked ICs Using Ternary Coded Simultaneous Bidirectional Signaling in Parallel Test Ports - researchr publication authors

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Iftikhar A. Soomro, Mohammad Samie, Ian K. Jennions. Test Time Reduction of 3-D Stacked ICs Using Ternary Coded Simultaneous Bidirectional Signaling in Parallel Test Ports. IEEE Trans. on CAD of Integrated Circuits and Systems, 39(12):5225-5237, 2020. [doi]

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