Reduced Pin-Count Test Strategy for 3D Stacked ICs Using Simultaneous Bi-Directional Signaling Based Time Division Multiplexing

Iftikhar A. Soomro, Mohammad Samie, Ian K. Jennions. Reduced Pin-Count Test Strategy for 3D Stacked ICs Using Simultaneous Bi-Directional Signaling Based Time Division Multiplexing. IEEE Access, 9:75892-75904, 2021. [doi]

@article{SoomroSJ21,
  title = {Reduced Pin-Count Test Strategy for 3D Stacked ICs Using Simultaneous Bi-Directional Signaling Based Time Division Multiplexing},
  author = {Iftikhar A. Soomro and Mohammad Samie and Ian K. Jennions},
  year = {2021},
  doi = {10.1109/ACCESS.2021.3081359},
  url = {https://doi.org/10.1109/ACCESS.2021.3081359},
  researchr = {https://researchr.org/publication/SoomroSJ21},
  cites = {0},
  citedby = {0},
  journal = {IEEE Access},
  volume = {9},
  pages = {75892-75904},
}