Functional test pattern generation for maximizing temperature in 3D IC chip stack - researchr publication authors

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Sudarshan Srinivasan, Sandip Kundu. Functional test pattern generation for maximizing temperature in 3D IC chip stack. In Keith A. Bowman, Kamesh V. Gadepally, Pallab Chatterjee, Mark M. Budnik, Lalitha Immaneni, editors, Thirteenth International Symposium on Quality Electronic Design, ISQED 2012, Santa Clara, CA, USA, March 19-21, 2012. pages 109-116, IEEE, 2012. [doi]

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