Sudarshan Srinivasan, Sandip Kundu. Functional test pattern generation for maximizing temperature in 3D IC chip stack. In Keith A. Bowman, Kamesh V. Gadepally, Pallab Chatterjee, Mark M. Budnik, Lalitha Immaneni, editors, Thirteenth International Symposium on Quality Electronic Design, ISQED 2012, Santa Clara, CA, USA, March 19-21, 2012. pages 109-116, IEEE, 2012. [doi]
@inproceedings{SrinivasanK12-0,
title = {Functional test pattern generation for maximizing temperature in 3D IC chip stack},
author = {Sudarshan Srinivasan and Sandip Kundu},
year = {2012},
doi = {10.1109/ISQED.2012.6187482},
url = {http://dx.doi.org/10.1109/ISQED.2012.6187482},
researchr = {https://researchr.org/publication/SrinivasanK12-0},
cites = {0},
citedby = {0},
pages = {109-116},
booktitle = {Thirteenth International Symposium on Quality Electronic Design, ISQED 2012, Santa Clara, CA, USA, March 19-21, 2012},
editor = {Keith A. Bowman and Kamesh V. Gadepally and Pallab Chatterjee and Mark M. Budnik and Lalitha Immaneni},
publisher = {IEEE},
isbn = {978-1-4673-1034-5},
}