Daniel L. Stasiak, Farnaz Mounes-Toussi, Salvatore N. Storino. A 440-ps 64-bit adder in 1.5-V/0.18-/spl mu/m partially depleted SOI technology. J. Solid-State Circuits, 36(10):1546-1552, 2001. [doi]
@article{StasiakMS01,
title = {A 440-ps 64-bit adder in 1.5-V/0.18-/spl mu/m partially depleted SOI technology},
author = {Daniel L. Stasiak and Farnaz Mounes-Toussi and Salvatore N. Storino},
year = {2001},
doi = {10.1109/4.953483},
url = {https://doi.org/10.1109/4.953483},
researchr = {https://researchr.org/publication/StasiakMS01},
cites = {0},
citedby = {0},
journal = {J. Solid-State Circuits},
volume = {36},
number = {10},
pages = {1546-1552},
}