Bit Serial Pattern Generation and Response Compaction Using Arithmetic Functions

Albrecht P. Stroele. Bit Serial Pattern Generation and Response Compaction Using Arithmetic Functions. In 16th IEEE VLSI Test Symposium (VTS 98), 28 April - 1 May 1998, Princeton, NJ, USA. pages 78-85, IEEE Computer Society, 1998. [doi]

Authors

Albrecht P. Stroele

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