Clock Skew Minimization in Multi-Voltage Mode Designs Using Adjustable Delay Buffers

Yu-Shih Su, Wing-Kai Hon, Cheng-Chih Yang, Shih-Chieh Chang, Yeong-Jar Chang. Clock Skew Minimization in Multi-Voltage Mode Designs Using Adjustable Delay Buffers. IEEE Trans. on CAD of Integrated Circuits and Systems, 29(12):1921-1930, 2010. [doi]

@article{SuHYCC10,
  title = {Clock Skew Minimization in Multi-Voltage Mode Designs Using Adjustable Delay Buffers},
  author = {Yu-Shih Su and Wing-Kai Hon and Cheng-Chih Yang and Shih-Chieh Chang and Yeong-Jar Chang},
  year = {2010},
  doi = {10.1109/TCAD.2010.2061654},
  url = {http://dx.doi.org/10.1109/TCAD.2010.2061654},
  researchr = {https://researchr.org/publication/SuHYCC10},
  cites = {0},
  citedby = {0},
  journal = {IEEE Trans. on CAD of Integrated Circuits and Systems},
  volume = {29},
  number = {12},
  pages = {1921-1930},
}