Pin accessibility evaluating model for improving routability of VLSI designs

Hong-Yan Su, Shinichi Nishizawa, Yan-Shiun Wu, Jun Shiomi, Yih-Lang Li, Hidetoshi Onodera. Pin accessibility evaluating model for improving routability of VLSI designs. In Massimo Alioto, Hai Helen Li, Jürgen Becker, Ulf Schlichtmann, Ramalingam Sridhar, editors, 30th IEEE International System-on-Chip Conference, SOCC 2017, Munich, Germany, September 5-8, 2017. pages 56-61, IEEE, 2017. [doi]

Abstract

Abstract is missing.