Scheduling of Iterative Algorithms on FPGA with Pipelined Arithmetic Unit - researchr publication

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Premysl Sucha, Zdenek Pohl, Zdenek Hanzálek. Scheduling of Iterative Algorithms on FPGA with Pipelined Arithmetic Unit. In 10th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2004), 25-28 May 2004, Toronto, Canada. pages 404-412, IEEE Computer Society, 2004. [doi]

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