Vertical integration after stacking (ViaS) process for low-cost and low-stress 3D silicon integration

Kuniaki Sueoka, Akihiro Horibe, T. Aoki, Sayuri Kohara, Kazushige Toriyama, Hiroyuki Mori, Yasumitsu Orii. Vertical integration after stacking (ViaS) process for low-cost and low-stress 3D silicon integration. In 2015 International 3D Systems Integration Conference, 3DIC 2015, Sendai, Japan, August 31 - September 2, 2015. IEEE, 2015. [doi]

@inproceedings{SueokaHAKTMO15,
  title = {Vertical integration after stacking (ViaS) process for low-cost and low-stress 3D silicon integration},
  author = {Kuniaki Sueoka and Akihiro Horibe and T. Aoki and Sayuri Kohara and Kazushige Toriyama and Hiroyuki Mori and Yasumitsu Orii},
  year = {2015},
  doi = {10.1109/3DIC.2015.7334608},
  url = {http://dx.doi.org/10.1109/3DIC.2015.7334608},
  researchr = {https://researchr.org/publication/SueokaHAKTMO15},
  cites = {0},
  citedby = {0},
  booktitle = {2015 International 3D Systems Integration Conference, 3DIC 2015, Sendai, Japan, August 31 - September 2, 2015},
  publisher = {IEEE},
  isbn = {978-1-4673-9385-0},
}