An analog PLL-based clock and data recovery circuit with high input jitter tolerance

Sam Yinshang Sun. An analog PLL-based clock and data recovery circuit with high input jitter tolerance. J. Solid-State Circuits, 24(2):325-330, April 1989. [doi]

@article{Sun89-2,
  title = {An analog PLL-based clock and data recovery circuit with high input jitter tolerance},
  author = {Sam Yinshang Sun},
  year = {1989},
  month = {April},
  doi = {10.1109/4.18592},
  url = {https://doi.org/10.1109/4.18592},
  researchr = {https://researchr.org/publication/Sun89-2},
  cites = {0},
  citedby = {0},
  journal = {J. Solid-State Circuits},
  volume = {24},
  number = {2},
  pages = {325-330},
}