Process variation aware data management for STT-RAM cache design - researchr publication authors

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Zhenyu Sun, Xiuyuan Bi, Hai Li. Process variation aware data management for STT-RAM cache design. In Naresh R. Shanbhag, Massimo Poncino, Pai H. Chou, Ajith Amerasekera, editors, International Symposium on Low Power Electronics and Design, ISLPED'12, Redondo Beach, CA, USA - July 30 - August 01, 2012. pages 179-184, ACM, 2012. [doi]

This author has not been identified. Look up 'Zhenyu Sun' in GoogleThis author has not been identified. Look up 'Xiuyuan Bi' in GoogleThis author has not been identified. Look up 'Hai Li' in Google

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