Zhenyu Sun, Xiuyuan Bi, Hai Li. Process variation aware data management for STT-RAM cache design. In Naresh R. Shanbhag, Massimo Poncino, Pai H. Chou, Ajith Amerasekera, editors, International Symposium on Low Power Electronics and Design, ISLPED'12, Redondo Beach, CA, USA - July 30 - August 01, 2012. pages 179-184, ACM, 2012. [doi]
@inproceedings{SunBL12,
title = {Process variation aware data management for STT-RAM cache design},
author = {Zhenyu Sun and Xiuyuan Bi and Hai Li},
year = {2012},
doi = {10.1145/2333660.2333706},
url = {http://doi.acm.org/10.1145/2333660.2333706},
researchr = {https://researchr.org/publication/SunBL12},
cites = {0},
citedby = {0},
pages = {179-184},
booktitle = {International Symposium on Low Power Electronics and Design, ISLPED'12, Redondo Beach, CA, USA - July 30 - August 01, 2012},
editor = {Naresh R. Shanbhag and Massimo Poncino and Pai H. Chou and Ajith Amerasekera},
publisher = {ACM},
isbn = {978-1-4503-1249-3},
}