The following publications are possibly variants of this publication:
- A Multiplying Delay-Locked Loop design with low jitter and high linearityJiahao Hu, Zhongxian Huang, BaoXing Duan, Qing Li, Ziqi Song, Dian He. icta3 2022: 38-39 [doi]
- A low jitter multiplying delay-locked loop with static phase offset elimination applied to time-to-digital converterJin Wu, Shuang Chen, Kang Hu, Lixia Zheng, Weifeng Sun. mj, 106:104926, 2020. [doi]
- Low-jitter DLL applied for two-segment TDCJin Wu, Youzhi Zhang, Rongqi Zhao, Kunpeng Zhang, Lixia Zheng, Weifeng Sun. iet-cds, 12(1):17-24, 2018. [doi]