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Test Architecture for Fine Grained Capture Power Reduction

Yi Sun, Hui Jiang, Lakshmi Ramakrishnan, Matan Segal, Kundan Nepal, Jennifer Dworak, Theodore W. Manikas, R. Iris Bahar. Test Architecture for Fine Grained Capture Power Reduction. In 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019, Genoa, Italy, November 27-29, 2019. pages 558-561, IEEE, 2019. [doi]

Authors

Yi Sun

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Hui Jiang

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Lakshmi Ramakrishnan

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Matan Segal

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Kundan Nepal

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Jennifer Dworak

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Theodore W. Manikas

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R. Iris Bahar

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