dd-Margin Reduction in a 0.6-to-1.0-V Cortex-M0 Processor

Xun Sun, Fahim ur Rahman, Venkata Rajesh Pamula 0001, Sung Kim, Xi Li, Naveen John, Visvesh S. Sathe 0001. dd-Margin Reduction in a 0.6-to-1.0-V Cortex-M0 Processor. J. Solid-State Circuits, 54(11):3215-3225, 2019. [doi]

Abstract

Abstract is missing.