Low Power Gate Resizing of Combinational Circuits by Buffer-Redistribution

Vijay Sundararajan, Keshab K. Parhi. Low Power Gate Resizing of Combinational Circuits by Buffer-Redistribution. In 18th Conference on Advanced Research in VLSI (ARVLSI 99), 21-24 March 1999, Atlanta, GA, USA. pages 170-185, IEEE Computer Society, 1999. [doi]

@inproceedings{SundararajanP99,
  title = {Low Power Gate Resizing of Combinational Circuits by Buffer-Redistribution},
  author = {Vijay Sundararajan and Keshab K. Parhi},
  year = {1999},
  doi = {10.1109/ARVLSI.1999.756047},
  url = {http://doi.ieeecomputersociety.org/10.1109/ARVLSI.1999.756047},
  researchr = {https://researchr.org/publication/SundararajanP99},
  cites = {0},
  citedby = {0},
  pages = {170-185},
  booktitle = {18th Conference on Advanced Research in VLSI (ARVLSI  99), 21-24 March 1999, Atlanta, GA, USA},
  publisher = {IEEE Computer Society},
  isbn = {0-7695-0056-0},
}