On-chip lightweight implementation of reduced NIST randomness test suite - researchr publication authors

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Vikram B. Suresh, Daniele Antonioli, Wayne P. Burleson. On-chip lightweight implementation of reduced NIST randomness test suite. In 2013 IEEE International Symposium on Hardware-Oriented Security and Trust, HOST 2013, Austin, TX, USA, June 2-3, 2013. pages 93-98, IEEE, 2013. [doi]

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