Vikram B. Suresh, Daniele Antonioli, Wayne P. Burleson. On-chip lightweight implementation of reduced NIST randomness test suite. In 2013 IEEE International Symposium on Hardware-Oriented Security and Trust, HOST 2013, Austin, TX, USA, June 2-3, 2013. pages 93-98, IEEE, 2013. [doi]
@inproceedings{SureshAB13,
title = {On-chip lightweight implementation of reduced NIST randomness test suite},
author = {Vikram B. Suresh and Daniele Antonioli and Wayne P. Burleson},
year = {2013},
doi = {10.1109/HST.2013.6581572},
url = {http://doi.ieeecomputersociety.org/10.1109/HST.2013.6581572},
researchr = {https://researchr.org/publication/SureshAB13},
cites = {0},
citedby = {0},
pages = {93-98},
booktitle = {2013 IEEE International Symposium on Hardware-Oriented Security and Trust, HOST 2013, Austin, TX, USA, June 2-3, 2013},
publisher = {IEEE},
isbn = {978-1-4799-0559-1},
}