Abstract is missing.
- Cloning Physically Unclonable FunctionsClemens Helfmeier, Christian Boit, Dmitry Nedospasov, Jean-Pierre Seifert. 1-6 [doi]
- Intellectual property protection for FPGA designs with soft physical hash functions: First experimental resultsStéphanie Kerckhof, François Durvaux, François-Xavier Standaert, Benoît Gérard. 7-12 [doi]
- Novel strong PUF based on nonlinearity of MOSFET subthreshold operationMukund Kalyanaraman, Michael Orshansky. 13-18 [doi]
- Localized electromagnetic analysis of RO PUFsDominik Merli, Johann Heyszl, Benedikt Heinz, Dieter Schuster, Frederic Stumpf, Georg Sigl. 19-24 [doi]
- Enhancing fault sensitivity analysis through templatesFilippo Melzani, Andrea Palomba. 25-28 [doi]
- Hardware implementations of the WG-5 cipher for passive RFID tagsMark Aagaard, Guang Gong, Rajesh K. Mota. 29-34 [doi]
- Adapting voltage ramp-up time for temperature noise reduction on memory-based PUFsMafalda Cortez, Said Hamdioui, Vincent van der Leest, Roel Maes, Geert Jan Schrijen. 35-40 [doi]
- Model building attacks on Physically Unclonable Functions using genetic programmingIndrasish Saha, Ratan Rahul Jeldi, Rajat Subhra Chakraborty. 41-44 [doi]
- BISA: Built-in self-authentication for preventing hardware Trojan insertionKan Xiao, Mohammad Tehranipoor. 45-50 [doi]
- A bulk built-in sensor for detection of fault attacksR. Possamai Bastos, Frank Sill Torres, Jean-Max Dutertre, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre. 51-54 [doi]
- Structural transformation for best-possible obfuscation of sequential circuitsLi Li 0021, Hai Zhou. 55-60 [doi]
- An efficient algorithm for identifying security relevant logic and vulnerabilities in RTL designsDavid W. Palmer, Parbati Kumar Manna. 61-66 [doi]
- WordRev: Finding word-level structures in a sea of bit-level gatesWenchao Li, Adria Gascón, Pramod Subramanyan, Wei Yang Tan, Ashish Tiwari, Sharad Malik, Natarajan Shankar, Sanjit A. Seshia. 67-74 [doi]
- On implementing trusted boot for embedded systemsObaid Khalid, Carsten Rolfes, Andreas Ibing. 75-80 [doi]
- Low-cost and area-efficient FPGA implementations of lattice-based cryptographyAydin Aysu, Cameron Patterson, Patrick Schaumont. 81-86 [doi]
- Design and implementation of rotation symmetric S-boxes with high nonlinearity and high DPA resilienceBodhisatwa Mazumdar, Debdeep Mukhopadhyay, Indranil Sengupta. 87-92 [doi]
- On-chip lightweight implementation of reduced NIST randomness test suiteVikram B. Suresh, Daniele Antonioli, Wayne P. Burleson. 93-98 [doi]
- Cycle-accurate information assurance by proof-carrying based signal sensitivity tracingYier Jin, Bo Yang, Yiorgos Makris. 99-106 [doi]
- On hardware Trojan design and implementation at register-transfer levelJie Zhang, Qiang Xu. 107-112 [doi]
- Malicious circuitry detection using fast timing characterization via test pointsSheng Wei, Miodrag Potkonjak. 113-118 [doi]
- Frontside laser fault injection on cryptosystems - Application to the AES' last round -Cyril Roscian, Jean-Max Dutertre, Assia Tria. 119-124 [doi]
- Side-Channel Analysis of MAC-KeccakMostafa M. I. Taha, Patrick Schaumont. 125-130 [doi]
- Pre-processing power traces with a phase-sensitive detectorPhilip Hodgers, Neil Hanley, Máire O'Neill. 131-136 [doi]
- Side channel modeling attacks on 65nm arbiter PUFs exploiting CMOS device noiseJeroen Delvaux, Ingrid Verbauwhede. 137-142 [doi]
- Stability analysis of a physical unclonable function based on metal resistance variationsJ. Ju, Ray Chakraborty, Charles Lamech, Jim Plusquellic. 143-150 [doi]
- Error-tolerant bit generation techniques for use with a hardware-embedded path delay PUFJim Aarestad, Jim Plusquellic, Dhruva Acharyya. 151-158 [doi]