Variation Aware Design of Post-Silicon Tunable Clock Buffer

Vikram B. Suresh, Wayne P. Burleson. Variation Aware Design of Post-Silicon Tunable Clock Buffer. In IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2014, Tampa, FL, USA, July 9-11, 2014. pages 1-6, IEEE, 2014. [doi]

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