B. Suresh, V. Visvanathan, R. S. Krishnan, H. S. Jamadagni. Application of Alpha Power Law Models to PLL Design Methodology. In 18th International Conference on VLSI Design (VLSI Design 2005), with the 4th International Conference on Embedded Systems Design, 3-7 January 2005, Kolkata, India. pages 768-773, IEEE Computer Society, 2005. [doi]
@inproceedings{SureshVKJ05,
title = {Application of Alpha Power Law Models to PLL Design Methodology},
author = {B. Suresh and V. Visvanathan and R. S. Krishnan and H. S. Jamadagni},
year = {2005},
url = {http://csdl.computer.org/comp/proceedings/vlsid/2005/2264/00/22640768abs.htm},
tags = {design},
researchr = {https://researchr.org/publication/SureshVKJ05},
cites = {0},
citedby = {0},
pages = {768-773},
booktitle = {18th International Conference on VLSI Design (VLSI Design 2005), with the 4th International Conference on Embedded Systems Design, 3-7 January 2005, Kolkata, India},
publisher = {IEEE Computer Society},
isbn = {0-7695-2264-5},
}