Hiroaki Suzuki, Hiroshi Making, Yoshio Matsuda. Novel VLIW code compaction method for a 3D geometry processor. In Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, CICC 2000, Orlando, FL, USA, May 21-24, 2000. pages 555-558, IEEE, 2000. [doi]
@inproceedings{SuzukiMM00,
title = {Novel VLIW code compaction method for a 3D geometry processor},
author = {Hiroaki Suzuki and Hiroshi Making and Yoshio Matsuda},
year = {2000},
doi = {10.1109/CICC.2000.852729},
url = {https://doi.org/10.1109/CICC.2000.852729},
researchr = {https://researchr.org/publication/SuzukiMM00},
cites = {0},
citedby = {0},
pages = {555-558},
booktitle = {Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, CICC 2000, Orlando, FL, USA, May 21-24, 2000},
publisher = {IEEE},
isbn = {0-7803-5809-0},
}