Kenichi Suzuki, Mitsuhiro Takeda, Atsushi Kamo, Hideki Asai. A Novel Application of Verilog-A to Modeling and Simulation of High-Speed Interconnects in Time/Frequency Transform-Domain. IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 85-A(2):395-398, 2002. [doi]
Abstract is missing.