Toshikazu Suzuki, Yoshinobu Yamagami, Ichiro Hatanaka, Akinori Shibayama, Hironori Akamatsu, Hiroyuki Yamauchi. A sub-0.5-V operating embedded SRAM featuring a multi-bit-error-immune hidden-ECC scheme. J. Solid-State Circuits, 41(1):152-160, 2006. [doi]
Abstract is missing.