Pianissimo: A Sub-mW Class DNN Accelerator with Progressive Bit-by-Bit Datapath Architecture for Adaptive Inference at Edge

Junnosuke Suzuki, Jaehoon Yu, Mari Yasunaga, Ángel López García-Arias, Yasuyuki Okoshi, Shungo Kumazawa, Kota Ando, Kazushi Kawamura, Thiem Van Chu, Masato Motomura. Pianissimo: A Sub-mW Class DNN Accelerator with Progressive Bit-by-Bit Datapath Architecture for Adaptive Inference at Edge. In 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Kyoto, Japan, June 11-16, 2023. pages 1-2, IEEE, 2023. [doi]

Authors

Junnosuke Suzuki

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Jaehoon Yu

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Mari Yasunaga

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Ángel López García-Arias

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Yasuyuki Okoshi

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Shungo Kumazawa

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Kota Ando

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Kazushi Kawamura

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Thiem Van Chu

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Masato Motomura

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