Junnosuke Suzuki, Jaehoon Yu, Mari Yasunaga, Ángel López García-Arias, Yasuyuki Okoshi, Shungo Kumazawa, Kota Ando, Kazushi Kawamura, Thiem Van Chu, Masato Motomura. Pianissimo: A Sub-mW Class DNN Accelerator with Progressive Bit-by-Bit Datapath Architecture for Adaptive Inference at Edge. In 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Kyoto, Japan, June 11-16, 2023. pages 1-2, IEEE, 2023. [doi]
@inproceedings{SuzukiYYGOKAKCM23,
title = {Pianissimo: A Sub-mW Class DNN Accelerator with Progressive Bit-by-Bit Datapath Architecture for Adaptive Inference at Edge},
author = {Junnosuke Suzuki and Jaehoon Yu and Mari Yasunaga and Ángel López García-Arias and Yasuyuki Okoshi and Shungo Kumazawa and Kota Ando and Kazushi Kawamura and Thiem Van Chu and Masato Motomura},
year = {2023},
doi = {10.23919/VLSITechnologyandCir57934.2023.10185293},
url = {https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185293},
researchr = {https://researchr.org/publication/SuzukiYYGOKAKCM23},
cites = {0},
citedby = {0},
pages = {1-2},
booktitle = {2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Kyoto, Japan, June 11-16, 2023},
publisher = {IEEE},
isbn = {978-4-86348-806-9},
}