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Ioannis L. Syllaios, Robert Bogdan Staszewski, Poras T. Balsara. Time-Domain Modeling of an RF All-Digital PLL. IEEE Trans. on Circuits and Systems, 55-II(6):601-605, 2008. [doi]
Possibly Related PublicationsThe following publications are possibly variants of this publication: VHDL Simulation and Modeling of an All-Digital RF TransmitterRobert B. Staszewski, Roman Staszewski, Poras T. Balsara. iwsoc 2005: 233-238 [doi] Multi-clock domain analysis and modeling of all-digital frequency synthesizersIoannis L. Syllaios, Poras T. Balsara. iscas 2011: 153-156 [doi] Time-Domain Modeling of a Phase-Domain All-Digital Phase-Locked Loop for RF ApplicationsIoannis L. Syllaios, Poras T. Balsara, Robert Bogdan Staszewski. cicc 2007: 861-864 [doi]
The following publications are possibly variants of this publication: