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Noboru Takagi, Akimitsu Hon-nami, Kyoichi Nakashima. Logical Model for Representing Uncertain Statuses of Multiple-Valued Logic Systems Realized by Min, Max and Literals. In ISMVL. pages 110-115, 1999. [doi]
Possibly Related PublicationsThe following publications are possibly variants of this publication: A Delay Model of Multiple-Valued Logic Circuits Consisting of Min, Max, and Literal OperationsNoboru Takagi. ieicet, 93-D(8):2040-2047, 2010. [doi] Logic for Static Hazard Detection of Multiple-Valued Logic Circuits with Tsum, Min, and LiteralsNoboru Takagi, Kyoichi Nakashima. ismvl 2002: 46 [doi]
The following publications are possibly variants of this publication: