High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree

Naofumi Takagi, Hiroto Yasuura, Shuzo Yajima. High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree. IEEE Transactions on Computers, 34(9):789-796, 1985.

Authors

Naofumi Takagi

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Hiroto Yasuura

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Shuzo Yajima

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