A Shared-Bus Control Mechanism and a Cache Coherence Protocol for a High-Performance On-Chip Multiprocessor

Masafumi Takahashi, Hiroyuki Takano, Emi Kaneko, Seigo Suzuki. A Shared-Bus Control Mechanism and a Cache Coherence Protocol for a High-Performance On-Chip Multiprocessor. In HPCA. pages 314-322, 1996. [doi]

@inproceedings{TakahashiTKS96,
  title = {A Shared-Bus Control Mechanism and a Cache Coherence Protocol for a High-Performance On-Chip Multiprocessor},
  author = {Masafumi Takahashi and Hiroyuki Takano and Emi Kaneko and Seigo Suzuki},
  year = {1996},
  url = {http://computer.org/proceedings/hpca/7237/72370314abs.htm},
  tags = {caching, protocol},
  researchr = {https://researchr.org/publication/TakahashiTKS96},
  cites = {0},
  citedby = {0},
  pages = {314-322},
  booktitle = {HPCA},
}