Formal Design Verification for Correctness of Pipelined Microprocessors with Out-of-order Instruction Execution

Takashi Takenaka, Junji Kitamichi, Teruo Higashino, Kenichi Taniguchi. Formal Design Verification for Correctness of Pipelined Microprocessors with Out-of-order Instruction Execution. In Proceedings of the 1999 Conference on Asia South Pacific Design Automation, January 18-21, 1999, Wanchai, Hong Kong. pages 177-180, IEEE, 1999. [doi]

Authors

Takashi Takenaka

This author has not been identified. Look up 'Takashi Takenaka' in Google

Junji Kitamichi

This author has not been identified. Look up 'Junji Kitamichi' in Google

Teruo Higashino

This author has not been identified. Look up 'Teruo Higashino' in Google

Kenichi Taniguchi

This author has not been identified. Look up 'Kenichi Taniguchi' in Google