Latency, Power and Performance Trade-Offs in Network-on-Chips by Link Microarchitecture Exploration - researchr publication authors

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Basavaraj Talwar, Shailesh Kulkarni, Bharadwaj Amrutur. Latency, Power and Performance Trade-Offs in Network-on-Chips by Link Microarchitecture Exploration. In VLSI Design 2009: Improving Productivity through Higher Abstraction, The 22nd International Conference on VLSI Design, New Delhi, India, 5-9 January 2009. pages 163-168, IEEE, 2009. [doi]

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