Basavaraj Talwar, Shailesh Kulkarni, Bharadwaj Amrutur. Latency, Power and Performance Trade-Offs in Network-on-Chips by Link Microarchitecture Exploration. In VLSI Design 2009: Improving Productivity through Higher Abstraction, The 22nd International Conference on VLSI Design, New Delhi, India, 5-9 January 2009. pages 163-168, IEEE, 2009. [doi]
@inproceedings{TalwarKA09,
title = {Latency, Power and Performance Trade-Offs in Network-on-Chips by Link Microarchitecture Exploration},
author = {Basavaraj Talwar and Shailesh Kulkarni and Bharadwaj Amrutur},
year = {2009},
doi = {10.1109/VLSI.Design.2009.55},
url = {http://dx.doi.org/10.1109/VLSI.Design.2009.55},
researchr = {https://researchr.org/publication/TalwarKA09},
cites = {0},
citedby = {0},
pages = {163-168},
booktitle = {VLSI Design 2009: Improving Productivity through Higher Abstraction, The 22nd International Conference on VLSI Design, New Delhi, India, 5-9 January 2009},
publisher = {IEEE},
isbn = {978-0-7695-3506-7},
}