Nagesh Tamarapalli, Prashanth Vallur, Sachin Kulkarni. Tutorial T5: High Performance Low Power Designs - Challenges and Best practices in Design, Verification and Test. In 28th International Conference on VLSI Design, VLSID 2015, Bangalore, India, January 3-7, 2015. pages 10-11, IEEE Computer Society, 2015. [doi]
@inproceedings{TamarapalliVK15,
title = {Tutorial T5: High Performance Low Power Designs - Challenges and Best practices in Design, Verification and Test},
author = {Nagesh Tamarapalli and Prashanth Vallur and Sachin Kulkarni},
year = {2015},
doi = {10.1109/VLSID.2015.113},
url = {http://doi.ieeecomputersociety.org/10.1109/VLSID.2015.113},
researchr = {https://researchr.org/publication/TamarapalliVK15},
cites = {0},
citedby = {0},
pages = {10-11},
booktitle = {28th International Conference on VLSI Design, VLSID 2015, Bangalore, India, January 3-7, 2015},
publisher = {IEEE Computer Society},
isbn = {978-1-4799-6658-5},
}