Timing-Error-Tolerant Network-on-Chip Design Methodology - researchr publication

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Rutuparna Tamhankar, Srinivasan Murali, Stergios Stergiou, Antonio Pullini, Federico Angiolini, Luca Benini, Giovanni De Micheli. Timing-Error-Tolerant Network-on-Chip Design Methodology. IEEE Trans. on CAD of Integrated Circuits and Systems, 26(7):1297-1310, 2007. [doi]

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