R. Tamura, I. Mori, N. Watanabe, Hiroki Koike, Tetsuo Endoh. Accurate error bit mode analysis of STT-MRAM chip with a novel current measurement module implemented to gigabit class memory test system. In Non-Volatile Memory Technology Symposium, NVMTS 2018, Sendai, Japan, October 22-24, 2018. pages 1-5, IEEE, 2018. [doi]
@inproceedings{TamuraMWKE18,
title = {Accurate error bit mode analysis of STT-MRAM chip with a novel current measurement module implemented to gigabit class memory test system},
author = {R. Tamura and I. Mori and N. Watanabe and Hiroki Koike and Tetsuo Endoh},
year = {2018},
doi = {10.1109/NVMTS.2018.8603113},
url = {https://doi.org/10.1109/NVMTS.2018.8603113},
researchr = {https://researchr.org/publication/TamuraMWKE18},
cites = {0},
citedby = {0},
pages = {1-5},
booktitle = {Non-Volatile Memory Technology Symposium, NVMTS 2018, Sendai, Japan, October 22-24, 2018},
publisher = {IEEE},
isbn = {978-1-5386-7783-4},
}