Weihang Tan, Antian Wang, Yunhao Xu, Yingjie Lao. Area-Efficient Pipelined VLSI Architecture for Polar Decoder. In 2020 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2020, Limassol, Cyprus, July 6-8, 2020. pages 352-357, IEEE, 2020. [doi]
Abstract is missing.