Table of Contents

• A Compact, Power Efficient, Self-Adaptive and PVT Invariant CMOS Relaxation OscillatorMounika Kelam, Balaji Yadav Battu, Zia Abbas. 1-6 [doi]
• Equivalence Checking Methods for Analog Circuits Using Continuous Reachable SetsAhmad Tarraf, Lars Hedrich, Niklas Kochdumper, Malgorzata Rechmal-Lesse, Markus Olbrich. 7-12 [doi]
• A 1.8V 8-Bit 500 MSPS Segmented Current Steering DAC with >66 dB SFDRSmrutilekha Samanta, Santanu Sarkar. 13-17 [doi]
• Enabling Optimal Power Generation of Flow Cell Arrays in 3D MPSoCs with On-Chip Switched Capacitor ConvertersHalima Najibi, Jorge Hunter, Alexandre Levisse, Marina Zapater, Miroslav Vasic, David Atienza. 18-23 [doi]
• Exploring a Machine Learning Approach to Performance Driven Analog IC PlacementYaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind K. Sharma, Wenbin Xu, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu. 24-29 [doi]
• Enhancing Real-Time Motion Estimation through Approximate High-Level SynthesisMarcos T. Leipnitz, Murilo R. Perleberg, Marcelo Schiavon Porto, Gabriel L. Nazar. 30-35 [doi]
• Inference and Energy Efficient Design of Deep Neural Networks for Embedded DevicesIoannis Galanis, Iraklis Anagnostopoulos, Chinh Nguyen, Guillermo Bares, Dona Burkard. 36-41 [doi]
• 3D-Sorter: 3D Design of a Resource-Aware Hardware Sorter for Edge Computing Platforms Under Area and Energy Consumption ConstraintsAmin Norollah, Zahra Kazemi, David Hély. 42-47 [doi]
• A Novel Single Event Upset Tolerant 12T Memory Cell for Aerospace ApplicationsSuraj Dohar, Siddharth R. K., Vasantha M. H., Nithin Kumar Y. B.. 48-53 [doi]
• NV-SP: A New High Performance and Low Energy NVM-Based Scratch PadAmeer Shalabi, Kolin Paul, Tara Ghasempouri, Jaan Raik. 54-59 [doi]
• 2-Output Spin Wave Programmable Logic GateAbdulqader Mahmoud, Frederic Vanderveken, Christoph Adelmann, Florin Ciubotaru, Sorin Cotofana, Said Hamdioui. 60-65 [doi]
• Bail on Balancing: An Alternative Approach to the Physical Design of Field-Coupled Nanocomputing CircuitsMarcel Walter, Robert Wille, Frank Sill Torres, Rolf Drechsler. 66-71 [doi]
• Fast Resilient-Aware Data Layout Organization for Resistive Computing SystemsBaogang Zhang, M. G. Sarwar Murshed, Faraz Hussain, Rickard Ewetz. 72-77 [doi]
• A CORDIC Based Configurable Activation Function for ANN ApplicationsGopal Raut, Shubham Rai, Santosh Kumar Vishvakarma, Akash Kumar 0001. 78-83 [doi]
• Hardware Optimized Approximate Adder with Normal Error DistributionRaunaq Nayar, Padmanabhan Balasubramanian, Douglas L. Maskell. 84-89 [doi]
• A Multi-grained Reconfigurable Accelerator for Approximate ComputingYirong Kan, Man Wu, Renyuan Zhang, Yasuhiko Nakashima. 90-95 [doi]
• Efficient Hardware Implementation of Artificial Neural Networks Using Approximate Multiply-Accumulate BlocksMohammadreza Esmali Nojehdeh, Levent Aksoy, Mustafa Altun. 96-101 [doi]
• Path-Spreading Search Algorithm and ASIP Approach for Connection Allocation in TDM-NoCsSeungseok Nam, Emil Matús, Sadia Moriam, Gerhard P. Fettweis. 102-107 [doi]
• On Leveraging Multi-threshold FinFETs for Design ObfuscationVinay C. Patil, Sandip Kundu. 108-113 [doi]
• Logic Locking Induced Fault AttacksMichaela Brunner, Michael Gruber, Michael Tempelmeier, Georg Sigl. 114-119 [doi]
• An Open-Source Area-Optimized ECEG Cryptosystem in HardwareNourhan Elhamawy, Maël Gay, Ilia Polian. 120-125 [doi]
• QUANTIFY: A Framework for Resource Analysis and Design Verification of Quantum CircuitsOumarou Oumarou, Alexandru Paler, Robert Basmadjian. 126-131 [doi]
• Advances in Molecular Quantum Computing: from Technological Modeling to Circuit DesignGiovanni Amedeo Cirillo, Giovanna Turvani, Mario Simoni, Mariagrazia Graziano. 132-137 [doi]
• Quantum Divide and Compute: Hardware Demonstrations and Noisy SimulationsThomas Ayral, François-Marie Le Régent, Zain Saleem, Yuri Alexeev, Martin Suchara. 138-140 [doi]
• Quantum Resource Counts for Operations Constructed from an Addition CircuitShaun Miller. 141-146 [doi]
• Exploiting On-Chip Routers to Store Dirty Cache Blocks in Tiled Chip Multi-processorsAbhijit Das 0002, Abhishek Kumar, John Jose, Maurizio Palesi. 147-152 [doi]
• SCRAMBLE: The State, Connectivity and Routing Augmentation Model for Building Logic EncryptionHadi Mardani Kamali, Kimia Zamiri Azar, Houman Homayoun, Avesta Sasan. 153-159 [doi]
• Lightweight and Trust-Aware Routing in NoC-Based SoCsSubodha Charles, Prabhat Mishra 0001. 160-167 [doi]
• Securing Network-on-Chip Using Incremental CryptographySubodha Charles, Prabhat Mishra 0001. 168-175 [doi]
• Design Automation for Field-Coupled NanotechnologiesMarcel Walter, Rolf Drechsler. 176-181 [doi]
• Efficient Techniques to Strongly Enhance the Virtual Prototype Based Design FlowVladimir Herdt, Rolf Drechsler. 182-187 [doi]
• Automated Design Understanding of SystemC-Based Virtual Prototypes: Data Extraction, Analysis and VisualizationMehran Goli, Rolf Drechsler. 188-193 [doi]
• LiNoVo: Longevity Enhancement of Non-Volatile Last Level Caches in Chip MultiprocessorsSukarn Agarwal, Hemangee K. Kapoor. 194-199 [doi]
• Locating Open-Channels in Octagon Networks on Chip-MicroprocessorsBiswajit Bhowmik, Santosh Biswas, Jatindra Kumar Deka, Bhargab B. Bhattacharya. 200-205 [doi]
• An Implementation of Pre-Quantized Random Demodulator Based on Amplitude-to-Pulse ConverterChenhui Feng, Hui Qian, Zhongfeng Wang. 206-211 [doi]
• A 2^7 -1 Low-Power Half-Rate 16-Gb/s Charge-Mode PRBS Generator in 1.2V, 65nm CMOSPrema Kumar Govindaswamy, Vijaya Sankara Rao Pasupureddi. 212-215 [doi]
• Efficient Organization of Digital Periphery to Support Integer Datatype for Memristor-Based CIMMahdi Zahedi, Mahta Mayahinia, Muath Abu Lebdeh, Stephan Wong, Said Hamdioui. 216-221 [doi]
• Reinforcement Learning Based Refresh Optimized Volatile STT-RAM CacheShashank Suman, Hemangee K. Kapoor. 222-227 [doi]
• Associative Thread Compaction for Efficient Control Flow Handling in GPGPUsYaohua Wang, Xiaowen Chen, Xiao Hu. 228-233 [doi]
• Near-Chip Dynamic Vision Filtering for Low-Bandwidth Pedestrian DetectionAnthony Bisulco, Fernando Cladera Ojeda, Volkan Isler, Daniel Dongyuel Lee. 234-239 [doi]
• Bus Width Aware Off-Chip Memory Access Minimization for CNN AcceleratorsSaurabh Tewari, Anshul Kumar, Kolin Paul. 240-245 [doi]
• Retraining and Regularization to Optimize Neural Networks for Stochastic ComputingJunseok Oh, Florian Neugebauer, Ilia Polian, John P. Hayes. 246-251 [doi]
• Tunable Voltage-Mode Subthreshold CMOS NeuronMargherita Ronchini, Milad Zamani, Hooman Farkhani, Farshad Moradi. 252-257 [doi]
• Leveraging 3D Vertical RRAM to Developing Neuromorphic Architecture for Pattern ClassificationBokyung Kim, Hai Li. 258-263 [doi]
• Distributed Kriging-Bootstrapped DNN Model for Fast, Accurate Seizure Detection from EEG SignalsIbrahim L. Olokodana, Saraju P. Mohanty, Elias Kougianos. 264-269 [doi]
• SafeController: Efficient and Transparent Control-Flow Integrity for RTL DesignSheikh Ariful Islam, Srinivas Katkoori. 270-275 [doi]
• Fast Linear Programming Optimization Using Crossbar-Based Analog AcceleratorLiuting Shang, Muhammad Adil, Ramtin Madani, Chenyun Pan. 276-281 [doi]
• Operational Quantum Annealers are Cursed by their Qubits Interconnection TopologiesDaniel Vert, Renaud Sirdey, Stéphane Louise. 282-287 [doi]
• How Many Trials Do We Need for Reliable NISQ Computing?Teruo Tanimoto, Shuhei Matsuo, Satoshi Kawakami, Yutaka Tabuchi, Masao Hirokawa, Koji Inoue. 288-290 [doi]
• Practical Error Modeling Toward Realistic NISQ SimulationTeruo Tanimoto, Shuhei Matsuo, Satoshi Kawakami, Yutaka Tabuchi, Masao Hirokawa, Koji Inoue. 291-293 [doi]
• A Quantum Pipeline for an Executable Quantum Instruction Set ArchitectureSuvadip Batabyal, Lovekush Sharma. 294-299 [doi]
• A Low-Cost Conflict-Free NoC Architecture for Heterogeneous Multicore SystemsYuwen Cui, Shakthi Prabhakar, Hui Zhao 0013, Saraju P. Mohanty, Juan Fang. 300-305 [doi]
• Exploration on Task Scheduling Strategy for CPU-GPU Heterogeneous Computing SystemJuan Fang, Jiaxing Zhang, Shuaibing Lu, Hui Zhao 0013. 306-311 [doi]
• Low-Power and Energy-Efficient Full Adders With Approximate Adiabatic Logic for Edge ComputingWu Yang, Himanshu Thapliyal. 312-315 [doi]
• R-Abax: A Radiation Hardening Legalisation Algorithm Satisfying TMR Spacing ConstraintsChristos Georgakidis, Christos P. Sotiriou, Nikolaos Sketopoulos, Milos Krstic, Oliver Schrape, Anselm Breitenreiter. 316-321 [doi]
• Enduring Non-Volatile L1 Cache Using Low-Retention-Time STTRAM CellsFarzane Rabiee, Mostafa Kajouyan, Newsha Estiri, Jordan Fluech, Mahdi Fazeli, Ahmad Patooghy. 322-327 [doi]
• Fast Cross-Layer Vulnerability Analysis of Complex Hardware DesignsJoseph Paturel, Angeliki Kritikakou, Olivier Sentieys. 328-333 [doi]
• A Novel Modular Multiplier for Isogeny-Based Post-Quantum CryptographyBo Wu, Jing Tian 0004, Xiao Hu, Zhongfeng Wang. 334-339 [doi]
• Enhanced Architecture for Computing Polynomials Using Unipolar Stochastic LogicShao-I Chu, Chen-En Hsieh, Yi-Ming Lee, Sayed Ahmad Salehi. 340-345 [doi]
• ACQuA: A Parallel Accelerator Architecture for Pure Functional ProgramsRicardo Coelho, Felipe Tanus, Álvaro F. Moreira, Gabriel L. Nazar. 346-351 [doi]
• Area-Efficient Pipelined VLSI Architecture for Polar DecoderWeihang Tan, Antian Wang, Yunhao Xu, Yingjie Lao. 352-357 [doi]
• Coupling Noise Mitigation using a Pass TransistorSelahattin Sayil, Subed Lamichhane, Kutay Sayil. 358-362 [doi]
• A Fast Transient Digitally Assisted Flash-Based Modular LDO for Sensor Nodes in WBANJitumani Sarma, Shatadal Chatterjee, Rakesh Biswas, Sounak Roy. 363-367 [doi]
• Cost-Effective Time-Redundancy Based Optimal Task Allocation for the Edge-Hub-Cloud SystemsAndreas Kouloumpris, Theocharis Theocharides, Maria K. Michael. 368-373 [doi]
• Vulnerability Analysis Against Fault Attack in terms of the Timing Behavior of Fault InjectionMahboube Fakhire, Ali Jahanian 0001. 374-379 [doi]
• Analyzing the Sensitivity of GPU Pipeline Registers to Single Events UpsetsJosie E. Rodriguez Condia, Marcio Gonçalves, José Rodrigo Azambuja, Matteo Sonza Reorda, Luca Sterpone. 380-385 [doi]
• Formal Verification of Constrained Arithmetic Circuits using Computer Algebraic ApproachTiankai Su, Atif Yasin, Sébastien Pillement, Maciej J. Ciesielski. 386-391 [doi]
• STA for Mixed Cyclic, Acyclic CircuitsStavros Simoglou, Christos P. Sotiriou, Dimitris Valiantzas, Nikolaos Sketopoulos. 392-397 [doi]
• Metal Stack and Partitioning Exploration for Monolithic 3D ICsNikolaos Sketopoulos, Christos P. Sotiriou, Vasilis Pavlidis. 398-403 [doi]
• Engineering a Standard Cell Library for an Industrial Router with ASAP7 PDKYuan-Dar Chung, Rung-Bin Lin. 404-409 [doi]
• Real Time Bayer Raw Video Projective Transformation System Using FPGAYongwen Zhuang, Dongmei Li. 410-414 [doi]
• Real-Time Minimum Energy Point Tracking Using a Predetermined Optimal Voltage Setting StrategyKhyati Kiyawat, Yutaka Masuda, Jun Shiomi, Tohru Ishihara. 415-421 [doi]
• Efficient Hardware Implementation of Discrete Wavelet Transform Based on Stochastic ComputingSayed Ahmad Salehi, Durjoy Deb Dhruba. 422-427 [doi]
• Action Evaluation Hardware Accelerator for Next-Generation Real-Time Reinforcement Learning in Emerging IoT SystemsJianchi Sun, Nikhilesh Sharma, Jacob Chakareski, Nicholas Mastronarde, Yingjie Lao. 428-433 [doi]
• ACA-CSU: A Carry Selection Based Accuracy Configurable Approximate Adder DesignAlish Kanani, Jigar Mehta, Neeraj Goel. 434-439 [doi]
• Secure-iGLU: A Secure Device for Noninvasive Glucose Measurement and Automatic Insulin Delivery in IoMT FrameworkAmit M. Joshi, Prateek Jain, Saraju P. Mohanty. 440-445 [doi]
• McPoRA: A Multi-chain Proof of Rapid Authentication for Post-Blockchain Based Security in Large Scale Complex Cyber-Physical SystemsAhmad Alkhodair, Saraju P. Mohanty, Elias Kougianos, Deepak Puthal. 446-451 [doi]
• Analyzing the Efficiency of Machine Learning Classifiers in Hardware-Based Malware DetectorsAbraham Peedikayil Kuruvila, Shamik Kundu, Kanad Basu. 452-457 [doi]
• A Solar Based Power Module for Battery-Less IoT Sensors Towards Sustainable Smart CitiesSaswat Kumar Ram, Shubham Chourasia, Banee Bandana Das, Ayas Kanta Swain, Kamalakanta Mahapatra, Saraju Mohanty. 458-463 [doi]
• Capacity Building Among European Stakeholders In the Areas of Cyber-Physical Systems, IoT & Embedded Systems: The SMART4ALL Digital Innovation Hub PerspectiveChristos P. Antonopoulos, Georgios Keramidas, Vassilis Tsakanikas, Evi Faliagka, Christos Panagiotou, Nikolaos S. Voros. 464-469 [doi]
• CPSoSaware: Cross-Layer Cognitive Optimization Tools & Methods for the Lifecycle Support of Dependable CPSoSGeorgios Keramidas, Christos P. Antonopoulos, Nikolaos Voros, Pekka Jääskeläinen, Marisa Catalán Cid, Evangelia I. Zacharaki, Apostolos P. Fournaris, Aris S. Lalos. 470-475 [doi]
• Towards Artificial-Intelligence-Based Cybersecurity for Robustifying Automated Driving Systems Against Camera Sensor AttacksChristos Kyrkou, Andreas Papachristodoulou, Andreas Kloukiniotis, Andreas Papandreou, Aris S. Lalos, Konstantinos Moustakas, Theocharis Theocharides. 476-481 [doi]
• Molecular MUX-Based Physical Unclonable FunctionsLulu Ge, Keshab K. Parhi. 482-487 [doi]
• A Synthesis Method for Power-Efficient Integrated Optical Logic Circuits Towards Light Speed ProcessingRyosuke Matsuo, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera, Akihiko Shinya, Masaya Notomi. 488-493 [doi]
• Current Comparator-Based Reconfigurable Adder and Multiplier on Hybrid Memristive CrossbarManobendra Nath Mondal, Susmita Sur-Kolay, Bhargab B. Bhattacharya. 494-499 [doi]
• PAG-IoT: A PUF and AEAD Enabled Trusted Hardware Gateway for IoT DevicesChristoph Frisch, Michael Tempelmeier, Michael Pehl. 500-505 [doi]
• Optimization and Evaluation of Energy-Efficient Mixed-Signal MFCC Feature Extraction ArchitectureYanMing Zhang, Xu Qiu, Qin Li, Fei Qiao, Qi Wei, Li Luo, Huazhong Yang. 506-511 [doi]
• A Mixed-Precision RISC-V Processor for Extreme-Edge DNN InferenceGianmarco Ottavi, Angelo Garofalo, Giuseppe Tagliavini, Francesco Conti 0001, Luca Benini, Davide Rossi. 512-517 [doi]
• Borrow Select Subtractor for Low Power and Area EfficiencyKeshav Govindarajan, V. S. Kanchana Bhaaskaran. 518-523 [doi]
• High Level Modeling of Memristive Crossbar ArraysMd. Adnan Zaman, Rajeev Joshi, Srinivas Katkoori. 524-529 [doi]
• Lightweight Ciphers on a 65 nm ASIC A Comparative Study on Energy ConsumptionBastian Richter, Amir Moradi 0001. 530-535 [doi]
• Guard-NoC: A Protection Against Side-Channel Attacks for MPSoCsCezar Reinbrecht, Abdullah Aljuffri, Said Hamdioui, Mottaqiallah Taouil, Bruno Forlin, Johanna Sepúlveda. 536-541 [doi]
• Regulating Degree of Adaptiveness for Performance-Centric NoC RoutingTuhin Subhra Das, Navonil Chatterjee, Prasun Ghosal. 542-547 [doi]
• Supporting QoS in AXI4 Based Communication ArchitectureBoqian Wang, Zhonghai Lu. 548-553 [doi]
• Mitigation of Tampering Attacks for MR-Based Thermal Sensing in Optical NoCsJun Zhou, Mengquan Li, Pengxing Guo, Weichen Liu. 554-559 [doi]
• DERauth: A Battery-Based Authentication Scheme for Distributed Energy ResourcesIoannis Zografopoulos, Charalambos Konstantinou. 560-567 [doi]
• Classification and Workload Balancing of Multi-threaded Application on Embedded PlatformsRakesh Kumar, Bibhas Ghoshal. 568-573 [doi]
• DRACO: Co-Optimizing Hardware Utilization, and Performance of DNNs on Systolic AcceleratorNandan Kumar Jha, Shreyas Ravishankar, Sparsh Mittal, Arvind Kaushik, Dipan Mandal, Mahesh Chandra. 574-579 [doi]
• Efficient Hardware Post Processing of Anchor-Based Object Detection on FPGAHui Zhang, Wei Wu, Yufei Ma, Zhongfeng Wang. 580-585 [doi]
• DoubtNet: Using Semantic Context to Enable Adaptive Inference for the IoTEric Homan, Chonghan Lee, Jack Sampson, John P. Sustersic, Vijaykrishnan Narayanan. 586-591 [doi]
• X-VS: Crossbar-Based Processing-in-Memory Architecture for Video SummarizationNagadastagiri Challapalle, Makesh Chandran, Sahithi Rampalli, Vijaykrishnan Narayanan. 592-597 [doi]
• iGLU: Non-Invasive Device for Continuous Glucose Measurement with IoMT FrameworkAmit M. Joshi, Prateek Jain, Saraju P. Mohanty. 598-599 [doi]
• Tot-Mon: A Real-Time Internet of Things Based Affective Framework for Monitoring InfantsAlhagie Sallah, Prabha Sundaravadivel. 600-601 [doi]
• A PUF Based CAN Security FrameworkTyler Cultice, Carson Labrado, Himanshu Thapliyal. 602-603 [doi]