Tomonori Tanaka, Kosuke Furuichi, Hiromu Uemura, Ryosuke Noguchi, Natsuyuki Koda, Koki Arauchi, Daichi Omoto, Hiromi Inaba, Keiji Kishine, Shinsuke Nakano, Masafumi Nogawa, Hideyuki Nosaka. 25-Gb/s clock and data recovery IC using latch-load combined with CML buffer circuit for delay generation with 65-nm CMOS. In IEEE International Symposium on Circuits and Systems, ISCAS 2017, Baltimore, MD, USA, May 28-31, 2017. pages 1-4, IEEE, 2017. [doi]
@inproceedings{TanakaFUNKAOIKN17,
title = {25-Gb/s clock and data recovery IC using latch-load combined with CML buffer circuit for delay generation with 65-nm CMOS},
author = {Tomonori Tanaka and Kosuke Furuichi and Hiromu Uemura and Ryosuke Noguchi and Natsuyuki Koda and Koki Arauchi and Daichi Omoto and Hiromi Inaba and Keiji Kishine and Shinsuke Nakano and Masafumi Nogawa and Hideyuki Nosaka},
year = {2017},
doi = {10.1109/ISCAS.2017.8050696},
url = {https://doi.org/10.1109/ISCAS.2017.8050696},
researchr = {https://researchr.org/publication/TanakaFUNKAOIKN17},
cites = {0},
citedby = {0},
pages = {1-4},
booktitle = {IEEE International Symposium on Circuits and Systems, ISCAS 2017, Baltimore, MD, USA, May 28-31, 2017},
publisher = {IEEE},
isbn = {978-1-4673-6853-7},
}