An Accurate Logic Threshold Voltages Determination Model for CMOS Gates to Facilitate Test Generation and Fault Simulation - researchr publication

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Jing-Jou Tang. An Accurate Logic Threshold Voltages Determination Model for CMOS Gates to Facilitate Test Generation and Fault Simulation. In 8th Asian Test Symposium (ATS 99), 16-18 November 1999, Shanghai, China. pages 81, IEEE Computer Society, 1999. [doi]

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