Kazuya Tanigawa, Tetsuo Hironaka. Design consideration for reconfigurable processor DS-HIE - Trade-off between performance and chip area. In International SoC Design Conference, ISOCC 2011, Jeju, South Korea, November 17-18, 2011. pages 187-190, IEEE, 2011. [doi]
@inproceedings{TanigawaH11,
title = {Design consideration for reconfigurable processor DS-HIE - Trade-off between performance and chip area},
author = {Kazuya Tanigawa and Tetsuo Hironaka},
year = {2011},
doi = {10.1109/ISOCC.2011.6138679},
url = {http://dx.doi.org/10.1109/ISOCC.2011.6138679},
researchr = {https://researchr.org/publication/TanigawaH11},
cites = {0},
citedby = {0},
pages = {187-190},
booktitle = {International SoC Design Conference, ISOCC 2011, Jeju, South Korea, November 17-18, 2011},
publisher = {IEEE},
isbn = {978-1-4577-0709-4},
}