Satoru Tanoi, Yasuhiro Tanaka, Tetsuya Tanabe, Akio Eta, Toshio Inada, Ryoji Hamazaki, Yoshio Ohtsuki, Masaru Uesugi. A 32-bank 256-Mb DRAM with cache and TAG. J. Solid-State Circuits, 29(11):1330-1335, November 1994. [doi]
@article{TanoiTTEIHOU94,
title = {A 32-bank 256-Mb DRAM with cache and TAG},
author = {Satoru Tanoi and Yasuhiro Tanaka and Tetsuya Tanabe and Akio Eta and Toshio Inada and Ryoji Hamazaki and Yoshio Ohtsuki and Masaru Uesugi},
year = {1994},
month = {November},
doi = {10.1109/4.328632},
url = {https://doi.org/10.1109/4.328632},
researchr = {https://researchr.org/publication/TanoiTTEIHOU94},
cites = {0},
citedby = {0},
journal = {J. Solid-State Circuits},
volume = {29},
number = {11},
pages = {1330-1335},
}