Design challenge in 3D NAND technology: A 4.8X area- and 1.3X power-efficient 20V charge pump using tier capacitors

T. Tanzawa, T. Murakoshi, T. Kamijo, T. Tanaka, J. J. McNeil, K. Duesman. Design challenge in 3D NAND technology: A 4.8X area- and 1.3X power-efficient 20V charge pump using tier capacitors. In IEEE Asian Solid-State Circuits Conference, A-SSCC 2016, Toyama, Japan, November 7-9, 2016. pages 165-168, IEEE, 2016. [doi]

Abstract

Abstract is missing.