Table of Contents

• A 3.2 mA-RX 3.5 mA-TX fully integrated SoC for Bluetooth Low EnergyMasayoshi Oshiro, Tatsuhiko Maruyama, Takashi Tokairin, Yuki Tuda, Tong Wang, Naotaka Koide, Yosuke Ogasawara, Tuan Thanh Ta, Hiroshi Yoshida, Kenichi Sami. 1-4 [doi]
• A 2GS/s 8b time-interleaved SAR ADC for millimeter-wave pulsed radar baseband SoCTakuji Miki, Toshiaki Ozeki, Jun-ichi Naka. 5-8 [doi]
• 20 mV input, 4.2 V output SIDO boost converter with low-power controller and adaptive switch size selector for thermoelectric energy harvestingYosuke Toyama, Taichi Ogawa, Takeshi Ueno, Tetsuro Itakura. 9-12 [doi]
• A high efficiency wide-load-range asynchronous boost converter with time-based dual-mode control for SSD applicationsKyoungjin Lee, Haneul Kim, Jehyung Yoon, Hyoung-Seok Oh, Byeong-ha Park, Ho-Jin Park, Yoonmyung Lee. 13-16 [doi]
• 2 28-nm pseudo 2-read/write dual-port SRAM using double pumping circuitryYuichiro Ishii, Makoto Yabuuchi, Yohei Sawada, Masao Morimoto, Yasumasa Tsukamoto, Yuta Yoshida, Ken Shibata, Toshiaki Sano, Shinji Tanaka, Koji Nii. 17-20 [doi]
• An 8-bit, 16 input, 3.2 pJ/op switched-capacitor dot product circuit in 28-nm FDSOI CMOSDaniel Bankman, Boris Murmann. 21-24 [doi]
• Time-domain neural network: A 48.5 TSOp/s/W neuromorphic chip optimized for deep learning and CMOS technologyDaisuke Miyashita, Shouhei Kousai, Tomoya Suzuki, Jun Deguchi. 25-28 [doi]
• A series-SSHI-Phi interface circuit for piezoelectric energy harvesting with 163% improvement in extracted power at off-resonanceChi-Huan Chen, Hung-Chen Chen, Yu-Shyang Huang, Ping-Hsuan Hsieh, Ping-Hsien Wu, Yi-Chung Shu. 29-32 [doi]
• An area-efficient wideband CMOS hall sensor system for camera autofocus systemsChih-Chan Tu, Kuan-Chung Chen, Tsung-Yu Wu, Tsung-Hsien Lin. 33-36 [doi]
• A time delay multiple integration linear CMOS image sensor for multispectral satellite telemetryKuan-Lin Liu, Chih-Cheng Hsieh, Sheng-Yeh Lai, Chin-Fong Chiu. 37-40 [doi]
• An inductive-coupling bus with collision detection scheme using magnetic field variation for 3-D network-on-chipsJunichiro Kadomoto, Tomoki Miyata, Hideharu Amano, Tadahiro Kuroda. 41-44 [doi]
• 2 sensor readout circuit with chopped VCO-based CTDSM in 40-nm CMOSChih-Chan Tu, Yu-Kai Wang, Tsung-Hsien Lin. 45-48 [doi]
• 56-Level programmable voltage detector in steps of 50mV for battery managementTeruki Someya, Kenichi Matsunaga, Hiroki Morimura, Takayasu Sakurai, Makoto Takamiya. 49-52 [doi]
• 93% Efficiency and 0.99 power factor in pseudo-linear LED driverShao-Wei Chiu, Chun-Chieh Kuo, Kai-Cheng Chuang, Wen-Hau Yang, Ke-Horng Chen, Chin-Long Wey, Ying-Hsi Lin, Jian-Ru Lin, Lsung-Yen Lsai, Jui-Lung Chen. 53-56 [doi]
• A high DR multi-channel stage-shared hybrid front-end for integrated power electronics controllerYuan Ren, Sai-Weng Sin, Chi-Seng Lam, Man-Chung Wong, Seng-Pan U, Rui Paulo Martins. 57-60 [doi]
• An OTA-C signal processing FPAA with 305 MHz GBW and integrated frequency-independent filter tuningDaniel DeDorigo, Yiannos Manoli. 61-64 [doi]
• A 9-bit 500-MS/s 6.0-mW dynamic pipelined ADC using time-domain linearized dynamic amplifiersLilan Yu, Masaya Miyahara, Akira Matsuzawa. 65-68 [doi]
• An 8-bit 1.25GS/s CMOS IF-sampling ADC with background calibration for dynamic distortionSi Chen, Boris Murmann. 69-72 [doi]
• A 10-b 800MS/s time-interleaved SAR ADC with fast timing-skew calibrationJeonggoo Song, Kareem Ragab, Xiyuan Tang, Nan Sun. 73-76 [doi]
• A 10-bit 1GS/s 4-way TI SAR ADC with tap-interpolated FIR filter based time skew calibrationLei Qiu, Kai Tang, Yan Zhu, Liter Siek, Yuanjin Zheng, Seng-Pan U. 77-80 [doi]
• A 0.9V 15fJ/conversion-step 8-bit 1.5GS/s two-step SAR ADCYao-Sheng Hu, Po-Chao Huang, Mi-Ti Yang, Shih-Wei Wu, Hsin-Shu Chen. 81-84 [doi]
• An improved 40 Gb/s CDR with jitter-suppression filters and phase-compensating interpolatorsXuqiang Zheng, Chun Zhang, Shuai Yuan, Feng Zhao, Shigang Yue, Ziqiang Wang, Fule Li, Zhihua Wang. 85-88 [doi]
• Fractional-N DPLL based low power clocking architecture for 1-14 Gb/s multi-standard transmitterMasum Hossain, Amlan Nag, Waleed El-Halwagy, A. K. M. Delwar Hossain, Aurangozeb. 89-92 [doi]
• A 4-GHz ΔΣ fractional-N frequency synthesizer with 2-dimensional quantization noise pushing and fractional spur elimination techniquesChun-Yu Lin, Tsung-Hsien Lin. 93-96 [doi]
• A 14.4Gb/s/pin 230fJ/b/pin/mm multi-level RF-interconnect for global network-on-chip communicationMajid Jalalifar, Gyung-Su Byun. 97-100 [doi]
• A digital MDLL using switched biasing technique to reduce low-frequency phase noiseChi-Huan Chiang, Chang-Cheng Huang, Ting-Kuei Kuan, Shen-Iuan Liu. 101-104 [doi]
• A 79GHz 2×2 MIMO PMCW radar SoC in 28nm CMOSDavide Guermandi, Qixian Shi, Andy Dewilde, Veerle Derudder, Ubaid Ahmad, Annachiara Spagnolo, André Bourdoux, Piet Wambacq, Wim Van Thillo. 105-108 [doi]
• An LO-buffer-less 60-GHz CMOS transmitter with oscillator pulling mitigationRui Wu, Jian Pang, Yuuki Seo, Kento Kimura, Seitaro Kawai, Shinji Sato, Satoshi Kondo, Tomohiro Ueno, Nurul Fajri, Yasuaki Takeuchi, Tatsuya Yamaguchi, Ahmed Musa, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa. 109-112 [doi]
• Low power FSK transceiver using ADPLL with direct modulation and integrated SPDT for BLE applicationDong Soo Lee, SeongJin Oh, Sungjin Kim, Cheolho Lee, ChangHun Song, Jungyeon Kim, WooSeob Kim, Hongjin Kim, Sang-Sun Yoo, Sukkyun Hong, Jeong-Woo Lee, YoungGun Pu, Kang-Yoon Lee. 113-116 [doi]
• Highly linear TIA for SAW-less FDD receiversGiacomo Pini, Danilo Manstretta, Rinaldo Castello. 117-120 [doi]
• Reprogrammable redundancy for cache Vmin reduction in a 28nm RISC-V processorBrian Zimmer, Pi-Feng Chiu, Borivoje Nikolic, Krste Asanovic. 121-124 [doi]
• On-chip supply power measurement and waveform reconstruction in a 28nm FD-SOI processor SoCMartin Cochet, Alberto Puggelli, Ben Keller, Brian Zimmer, Milovan Blagojevic, Sylvain Clerc, Philippe Roche, Jean-Luc Autran, Borivoje Nikolic. 125-128 [doi]
• A 0.35V 1.3pJ/cycle 20MHz 8-bit 8-tap FIR core based on wide-pulsed-latch pipelinesWei Jin, Seongjong Kim, Weifeng He, Zhigang Mao, Mingoo Seok. 129-132 [doi]
• 2 neural network engine with stream architecture and resonant clock meshShengshuo Lu, Zhengya Zhang, Marios C. Papaefthymiou. 133-136 [doi]
• Area-efficient one-cycle correction scheme for timing errors in flip-flop based pipelinesJongeun Koo, Eunwoo Song, Eunhyeok Park, Dongyoung Kim, Junki Park, Sungju Ryu, Sungjoo Yoo, Jae-Joon Kim. 137-140 [doi]
• A 5.1Gb/s 60.3fJ/bit/mm PVT tolerant NoC transceiverVishal Vinayak Kulkarni, Wei Yi Lim, Bin Zhao, Dan Lei Yan, Yu-Shun Wang, Jun Zhou, Muthukumaraswamy Annamalai Arasu. 141-144 [doi]
• 2 60dB SNDR 100MS/s reference error calibrated SAR ADC with 3pF decoupling capacitance for reference voltagesChi-Hang Chan, Yan Zhu 0001, Iok-Meng Ho, Wai-Hong Zhang, Chon-Lam Lio, Seng-Pan U, Rui Paulo Martins. 145-148 [doi]
• A 12-bit 200kS/s subranging SAR ADC with an energy-curve reshape techniqueYao-Sheng Hu, Kai-Yue Lin, Hsin-Shu Chen. 149-152 [doi]
• A 16 bit linear passive-charge-sharing SAR ADC in 55nm CMOSMark Maddox, Baozhen Chen, Michael C. W. Coln, Ron Kapusta, Junhua Shen, Lalinda Fernando. 153-156 [doi]
• A 12 bit 150 MS/s 1.5 mW SAR ADC with adaptive radix DAC in 40 nm CMOSKwuang-Han Chang, Chih-Cheng Hsieh. 157-160 [doi]
• A 4.86 mW 15-bit 22.5 MS/s pipelined ADC with 74 dB SNDR in 90 nm CMOS using averaging correlated level shifting techniqueTsung-Chih Hung, Tai-Haur Kuo. 161-164 [doi]
• Design challenge in 3D NAND technology: A 4.8X area- and 1.3X power-efficient 20V charge pump using tier capacitorsT. Tanzawa, T. Murakoshi, T. Kamijo, T. Tanaka, J. J. McNeil, K. Duesman. 165-168 [doi]
• Design of non-contact 2Gb/s I/O test methods for high bandwidth memory (HBM)Hyunui Lee, Sukyong Kang, Hye-Seung Yu, Won-Joo Yun, Jae-Hun Jung, Sungoh Ahn, Wang-Soo Kim, Beomyong Kil, Yoo-Chang Sung, Sang-Hoon Shin, Yong Sik Park, Yong Hwan Kim, Kyung-Woo Nam, Indal Song, Kyomin Sohn, Yong-Cheol Bae, Jung Hwan Choi, Seong-Jin Jang, Gyo-Young Jin. 169-172 [doi]
• A 0.3 pJ/access 8T data-aware SRAM utilizing column-based data encoding for ultra-low power applicationsAnh-Tuan Do, Seyed Mohammad Ali Zeinolabedin, Tony Tae-Hyoung Kim. 173-176 [doi]
• Reconfigurable, conditional pre-charge SRAM: Lowering read power by leveraging data statisticsChuhong Duan, Andreas J. Gotterba, Mahmut E. Sinangil, Anantha P. Chandrakasan. 177-180 [doi]
• A double-tail sense amplifier for low-voltage SRAM in 28nm technologyPi-Feng Chiu, Brian Zimmer, Borivoje Nikolic. 181-184 [doi]
• A 64-Kb 0.37V 28nm 10T-SRAM with mixed-Vth read-port and boosted WL scheme for IoT applicationsHidehiro Fujiwara, Yen-Huei Chen, Chih-Yu Lin, Wei-Cheng Wu, Dar Sun, Shin-Rung Wu, Hung-Jen Liao, Jonathan Chang. 185-188 [doi]
• A 2.34μJ/scan acoustic power scalable charge-redistribution pMUT interface system with on-chip aberration compensation for portable ultrasonic applicationsJudyta Tillak, Sina Akhbari, Nimesh Shah, Ljubomir Radakovic, Liwei Lin, Jerald Yoo. 189-192 [doi]
• An EEG-NIRS ear-module SoC for wearable drowsiness monitoring systemUnsoo Ha, Hoi-Jun Yoo. 193-196 [doi]
• An integrated CMOS optical sensing chip for multiple bio-signal detectionsAlbert Yen-Chih Chiou, Sung-En Hsieh, Yan-Quan Pan, Chia-Chi Kuo, Chih-Cheng Hsieh. 197-200 [doi]
• A 1.1mW hybrid OFDM ground effect-resilient body coupled communication transceiver for head and body area networkWala Saadeh, Haneen Alsuradi, Muhammad Awais Bin Altaf, Jerald Yoo. 201-204 [doi]
• A 83% peak efficiency 1.65 V to 11.4V dynamic voltage scaling supply for electrical stimulation applications in standard 0.18μm CMOS processLei Yao, I. Made Darmayuda, Yuan Gao. 205-208 [doi]
• A 13.56 MHz, 162 mW magnetically coupled digital rectifier with 94% VCR, 96% PCE over 50-to-5k Ω load range, and embedded 80 kbps DBPSK demodulator for biomedical applicationsHugo Cruz, Shuenn-Yuh Lee, Ching-Hsing Luo. 209-212 [doi]
• All-digital single-inductor multiple-output DC-DC converter with over 65.3% efficiency in 1 uW to 50 mW load range and 86.3% peak efficiencyManabu Yamada, Nam Binh Tran, Takayuki Miyazaki, Yoshiaki Yoshihara, Ryuichi Fujimoto. 213-216 [doi]
• Multiple-loop design technique for high-performance low dropout regulatorQuoc-Hoang Duong, Jeong-Woon Kong, Hyeon-Seok Shin, Huy-Hieu Nguyen, Pan-Jong Kim, Yu-Seok Ko, Hwa-Yeoul Yu, Ho-Jin Park. 217-220 [doi]
• A 90nA quiescent current 1.5V-5V 50mA asynchronous folding LDO using dual loop controlJun Liu, Troy Bryant, Nima Maghari, Jeffery Morroni. 221-224 [doi]
• A 0.38-μW stand-by power, 50-nA-to-1-mA load current range DC-DC converter with self-biased linear regulator for ultra-low power battery managementToshihiro Ozaki, Tetsuya Hirose, Hiroki Asano, Nobutaka Kuroki, Masahiro Numa. 225-228 [doi]
• An area efficient single-cycle xVDD sub-Vth on-chip boost scheme in 28 nm FD-SOIBabak Mohammadi, Oskar Andersson, Xiao Luo, Masoud Nouripayam, Joachim Neves Rodrigues. 229-232 [doi]
• A 32.75-Gb/s voltage mode transmitter with 3-tap FFE in 16nm CMOSKok Lim Chan, Kee Hian Tan, Yohan Frans, Jay Im, Parag Upadhyaya, Siok-Wei Lim, Arianne Roldan, Nakul Narang, Chin Yang Koay, Hongyuan Zhao, Ken Chang. 233-236 [doi]
• A model predictive control equalization transmitter for asymmetric interfaces in 28nm FDSOITaehwan Kim, Pavan Bhargava, Vladimir Stojanovic. 237-240 [doi]
• A 6-to-32 Gb/s voltage-mode transmitter with scalable supply, voltage swing, and pre-emphasis in 65-nm CMOSWoo-Rham Bae, Haram Ju, Kwanseo Park, Deog Kyoon Jeong. 241-244 [doi]
• All-synthesizable 6Gbps voltage-mode transmitter for serial linkYoung-Ho Choi, Kihwan Seong, Byungsub Kim, Jae-Yoon Sim, Hong June Park. 245-248 [doi]
• A 5-8 Gb/s low-power transmitter with 2-tap pre-emphasis based on toggling serializationSung-Geun Kim, Tongsung Kim, Dae Hyun Kwon, Woo-Young Choi. 249-252 [doi]
• A 305mV-850mV 400μW 45GSamples/J reconfigurable compressive sensing engine with early-termination for ultra-low energy target detection in 14nm tri-gate CMOSSudhir Satpathy, Sanu Mathew, Vikram Suresh, Mark Anders, Gregory K. Chen, Himanshu Kaul, Amit Agarwal, Steven Hsu, Ram Krishnamurthy, Vivek De. 253-256 [doi]
• A 34pJ/level pixel depth-estimation processor with shifter-based pipelined architecture for mobile user interfaceSungpill Choi, Seongwook Park, Hoi-Jun Yoo. 257-260 [doi]
• A low-power real-time hidden Markov model accelerator for gesture user interface on wearable devicesSeongrim Choi, Jaemin Hwang, Suhwan Cho, Ara Kim, Byeong-Gyu Nam. 261-264 [doi]
• A 41.3pJ/26.7pJ per neuron weight RBM processor for on-chip learning/inference applicationsChang-Hung Tsai, Wan-Ju Yu, Wing Hung Wong, Chen-Yi Lee. 265-268 [doi]
• A low-power calibration-free fractional-N digital PLL with high linear phase interpolatorFan Yang, Hangyan Guo, Runhua Wang, Zherui Zhang, Junhua Liu, Huailin Liao. 269-272 [doi]
• A technique for in-band phase noise reduction in fractional-N frequency synthesizersChun-Ping Wang, Tai-Cheng Lee. 273-276 [doi]
• A 1.9mW 750kb/s 2.4GHz F-OOK transmitter with symmetric FM template and high-point modulation PLLYining Zhang, Ranran Zhou, Woogeun Rhee, Zhihua Wang. 277-280 [doi]
• Lossless inductor current control in envelope tracking supply modulator with self-allocation of energy for optimzation of efficiency and EVMShang-Hsien Yang, Ke-Horng Chen, Chin-Long Wey, Ying-Hsi Lin, Jian-Ru Lin, Tsung-Yen Tsai. 281-284 [doi]
• A single-event upset robust, 2.2 GHz to 3.2 GHz, 345 fs jitter PLL with triple-modular redundant phase detector in 65 nm CMOSJeffrey Prinzie, Michiel Steyaert, Paul Leroux, Jorgen Christiansen, Paulo Moreira. 285-288 [doi]
• Triple-mode photovoltaic power management: Achieving high efficiency against harvesting and load variabilityJiangyi Li, Jae-sun Seo, Ioannis Kymissis, Mingoo Seok. 289-292 [doi]
• A single-inductor dual-input dual-output (SIDIDO) power management with sequential pulse-skip modulation for battery/PV hybrid systemsHui-Hsuan Lee, Po-Hung Chen. 293-296 [doi]
• An isolated PoR based pulse generator for TEG energy harvesting with minimum startup of 150 mV and maximum series resistance of 600 ΩAbhik Das, Yuan Gao, Tony T. Kim. 297-300 [doi]
• Ultra-low voltage ripple in DC-DC boost converter by the pumping capacitor and wire inductance techniqueChen-Fan Tang, Ke-Horng Chen, Chin-Long Wey, Ying-Hsi Lin, Jian-Ru Lin, Tsung-Yen Tsai. 301-304 [doi]
• A piezoelectric vibration energy harvesting system with improved power extraction capabilityYin-Jyun Hu, I-Chou Chen, Tsung-Heng Tsai. 305-308 [doi]
• nd order fully-passive noise-shaping SAR ADC with embedded passive gainZhijie Chen, Masaya Miyahara, Akira Matsuzawa. 309-312 [doi]
• A fine-resolution pulse-shrinking time-to-digital converter with completion detection utilizing built-in offset pulseTetsuya Iizuka, Takehisa Koga, Toru Nakura, Kunihiro Asada. 313-316 [doi]
• A 91.2dB SNDR 66.2fJ/conv. dynamic amplifier based 24kHz ΔΣ modulatorBeichen Zhang, Runjiang Dou, Liyuan Liu, Nanjian Wu. 317-320 [doi]
• A 79dB SNDR, 10MHz BW, 675MS/s open-loop time-based ADC employing a 1.15ps SAR-TDCWaleed El-Halwagy, P. Mousavi, Masum Hossain. 321-324 [doi]
• A 50 MHz bandwidth 54.2 dB SNDR reference-free stochastic ADC using VCO-based quantizersHyuk Sun, Jason Muhlestein, Spencer Leuenberger, Kazuki Sobue, Koichi Hamashita, Un-Ku Moon. 325-328 [doi]
• A 65-nm 0.35-V 7.1-μW memory-less adaptive PCG processor for wearable long-term cardiac monitoringChao Wang, Jianmin Zhang, Jun Zhou, Xin Liu, Ru San Tan, Liang Zhong, Kevin C. T. Chai. 329-332 [doi]
• A 28 nm CMOS 7.04 Gsps polar digital front-end processor for 60 GHz transmitterYanxiang Huang, Chunshu Li, Khaled Khalaf, André Bourdoux, Julien Verschueren, Qixian Shi, Piet Wambacq, Sofie Pollin, Wim Dehaene, Liesbet Van der Perre. 333-336 [doi]
• A 7.72 Gb/s LDPC-CC decoder with overlapped architecture for pre-5G wireless communicationsChia-Lung Lin, Rong-Jie Liu, Chih-Lung Chen, Hsie-Chia Chang, Chen-Yi Lee. 337-340 [doi]
• 1.68μJ/signature-generation 256-bit ECDSA over GF(p) signature generator for IoT devicesMasato Tamura, Makoto Ikeda. 341-344 [doi]
• A 32.9% PAE, 15.3 dBm, 21.6-41.6 GHz power amplifier in 65nm CMOS using coupled resonatorsHaikun Jia, Clarissa C. Prawoto, Baoyong Chi, Zhihua Wang, C. Patrick Yue. 345-348 [doi]
• A 16-43 GHz low-noise amplifer with 2.5-4.0 dB noise figureZhe Chen, Hao Gao, Domine M. W. Leenaerts, Dusan M. Milosevic, Peter G. M. Baltus. 349-352 [doi]
• A 7.9-GHz transformer-feedback quadrature VCO with a noise-shifting coupling networkBingwei Jiang, Chixiao Chen, Junyan Ren, Howard C. Luong. 353-356 [doi]
• Transformer-based varactor-less 96GHz-110GHz VCO and 89GHz-101GHz QVCO in 65nm CMOSXiaolong Liu, Chixiao Chen, Junyan Ren, Howard C. Luong. 357-360 [doi]